1. Field of the Invention
The present invention relates to a control loop in a power converter. In particular, the present invention relates to dynamically adjusting the switching frequency in a control loop of a power converter to provide a fast response to output transients.
2. Discussion of the Related Art
In a power converter, the output capacitor is a key factor in achieving a high power density. There are two main design considerations for an output capacitor: (a) steady state voltage ripple and (b) voltage spike during a transient. In a conventional power converter, the total output capacitance is mainly designed for transient response. Good transient response is normally achieved by optimizing the bandwidth of the power converter's control loop. However, due to non-linearity, a higher bandwidth does not always result in a better transient response. This can be illustrated, for example, by a peak current mode-controlled power converter.
FIG. 1(a) is a schematic diagram showing single-phase circuit configuration 100 for one type of power converter. As shown in FIG. 1(a), circuit configuration 100 includes a control module 101 receiving an input voltage Vin and providing clock signals 102a and 102b, which drive switch 103 (“top-side switch”) and switch 104 (“bottom-side switch”), respectively. The operations of top-side switch 103 and bottom-side switch 104 transfer energy to output capacitor 106 through output inductor 105. Based on feedback signal (VFB), control module 101 operates to maintain output voltage VO at a steady state value. In some power converters, multiple sets of inductors and top-side and bottom-side switches may be used in a “multi-phase” configuration to drive a common output voltage.
FIG. 1(b) shows the waveforms of output voltage (VO), the output current (IO), and the switching node signal (SW), in response to a step increase in load current of 15 A. In the power converter of FIG. 1(a), the design parameters are: (a) a 12-volt input voltage (Vin), (b) a 1-volt nominal output voltage (VO), (c) a 400 kHz switching frequency (fSW), (d) a 250 nH inductor (L), and (e) a 860 μF output capacitance (COUT), provided by two 330 μF/9 mΩ tantalum polymer capacitors, and two 100 μF/2 mΩ ceramic capacitors. The control loop bandwidth is around 60 kHz with 72° phase margin. As shown in FIG. 1(a), at time t=500 μs, the output load current increases by a 15 A step. Because the step current increase occurs immediately after the top-side switch is turned off, output voltage VO on the output capacitor drops rapidly to 0.92 volts until the top-side switch turns on again at the beginning of the next switching cycle (t=502.5 μs, about 2.3 μs later). During the switching cycle delay, the feedback control loop provides no help reducing the voltage drop at the output capacitor. The situation is more acute with small duty-cycle operation, as shown in FIG. 1.
A non-linear control scheme may reduce the switching cycle delay. In the non-linear control loop a threshold voltage is selected. When the output voltage falls below the threshold voltage, a voltage undershoot condition is deemed occurred. When the voltage undershoot condition is detected, the top-side switch is immediately turned on, rather than waiting for the beginning of the next switching cycle. There are, however, two drawbacks in this method. First, the monitored threshold voltage is sensitive to both component values and the layout. Second, the nonlinear control scheme may interact with one or more other control loops (e.g., a linear control loop) to create undesired oscillations. These drawbacks introduce unreliability in conventional designs.